Transistors are one of the major components of semiconductor devices. A transistor is comprised of three electrodes which are often referred to as a source, a drain, and a gate. The gate overlies a channel region which links the source and drain. Typically, the source and drain are formed in a single crystal silicon substrate by doping selected portions of the substrate. The gate is ordinarily formed from polycrystalline silicon, or polysilicon, which is deposited over the substrate. While these conventional bulk transistors (i.e. transistors formed in a bulk substrate) revolutionized semiconductor devices, new transistor applications and demands of increased performance and decreased size have led semiconductor manufacturers to develop new methods of forming transistors. One such method involves using polysilicon or amorphous silicon to form all electrodes of the transistor. These silicon transistors are also referred to as thin-film transistors (TFTs).
Thin-film transistors have several advantages over conventional bulk transistors. One significant advantage is that TFTs have the potential to be built one above the other, whereas bulk transistors are limited to fabrication within one level of a semiconductor device. Fabricating multilevel transistors enables the size of a semiconductor device to be substantially reduced while meeting the circuit performance demand. Another advantage is that TFTs are less susceptible to latch-up phenomenon and soft errors caused by incident alpha particles. One reason TFTs are more immune to soft errors is that the integration of TFTs into large scale circuits typically results in a larger capacitance. Another reason TFTs are less susceptible to the above problems is because TFTs are most often formed on an insulating layer rather than on a conducting or semiconducting substrate. Bulk transistors have channel regions which are contained within a very large semiconductor substrate material. Therefore, electrical phenomena occurring in the substrate have the potential to also influence the channel region. Channel regions in TFTs are usually isolated from the substrate by a dielectric material such that electrical effects in the substrate have no effect on the channel region.
Thin-film transistors are being explored for use in a number of integrated circuit semiconductor devices including flat panel or active matrix displays and MOS (metal oxide semiconductor) structures. Applications such as these sometimes require a high density of transistors. The use of TFTs is one appropriate way of achieving more dense circuitry, for example by fabricating multiple levels of thin-film transistors. But as the number of levels in a semiconductor device increases, so does fabrication complexity. Another problem with using conventional TFTs to increase transistor density is that many applications, particularly display applications, cannot utilize multiple layers of transistors. To avoid process complexity and limitations imposed by multiple layer transistors, some semiconductor manufacturers are focusing on increasing transistor density by reducing the size of individual transistors. However, most TFT structures have a horizontal orientation which results in transistors occupying a relatively large area within the device. Although existing TFT structures are very thin, as the name suggests, the horizontal dimensions or area of many TFTs are typically larger than existing bulk transistors due to the need to control short channel phenomena. Thus, the use of TFTs does not necessarily result in a smaller device.
Another problem associated with existing TFT structures, and also with existing bulk transistors, is channel length control. As mentioned above, most existing TFTs, and bulk transistors, are horizontal or planar structures having a horizontally oriented gate overlying a horizontally oriented channel region. Because many fabrication processes are self-aligned processes, the channel length is determined by the length of the gate. Typically, the gate is used to mask the channel region from dopants during formation of self-aligned (actually gate-aligned) source and drain regions. Thus, the distance between the source and drain regions, in other words the channel length, is determined by the gate dimension. In manufacturing, the gate dimension of a planar transistor can vary up to 20 percent in any given batch of devices. With such a variance in gate dimensions and therefore channel length, electrical characteristics and overall device performance are difficult to control.
Yet another problem with known TFTs is that many of the proposed TFT structures and fabrication processes employ amorphous, or non-crystalline, silicon as an electrode material, particularly for N-channel transistors used in active matrix display applications. However, digital circuit applications for TFTs require a higher carrier mobility than that provided by amorphous silicon, which is frequently used in active matrix display transistors. An additional disadvantage in using amorphous silicon in TFTs is that amorphous silicon deposition techniques are complex and not widely understood.
Therefore, a need exists for an improved semiconductor device, and more specifically for a semiconductor device having a thin-film transistor which has reduced transistor area, has highly controllable channel length, and is readily manufacturable.